Gate dielectric breakdown in the time-scale of ESD events

نویسندگان

  • Bonnie E. Weir
  • Che-Choi Leung
  • Paul J. Silverman
  • Muhammad A. Alam
چکیده

Transmission line pulse (TLP) measurements are used to demonstrate that oxynitride breakdown projections from DC measurements using conventional area and voltage-scaling techniques can be extended to the nanosecond timescale. ESD protection systems can thus be designed to prevent dielectric breakdown. Important concepts in gate dielectric breakdown such as the anode–hole injection model and area and statistical effects are discussed and applied to the nanosecond regime. 2004 Elsevier Ltd. All rights reserved.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Transmission Line MBdel Testing of Top-Gate Amorphous SiliconThin Film Transistors

In this paper, for the first time Transmission Line Model (TLM) characterization is used to analyze ESD events in amorphous silicon thin film transistors (a-Si:H TFT). It will be ,shown that, above an ESD degradation threshold voltage, deterioration of electrical characteristics sets in, and that above another ESD failure threshold voltage, dielectric breakdown occurs. Electrical simulations of...

متن کامل

Nanoscale Physical Analysis of Localized Breakdown Events in HfO2/SiOX Dielectric Stacks: A Correlation study of STM induced BD with C-AFM and TEM

The study of scanning tunneling microscopy (STM) induced localized dielectric degradation and polarity dependent breakdown (BD) in HfO2/SiOx dielectric stacks is presented in this work, together with a correlated investigation of the BD locations by transmission electron microscopy (TEM). The localized dielectric BD events are also analysed using conductive-atomic force microscopy (C-AFM). The ...

متن کامل

Analysis of Nonuniform ESD Current Distribution in Deep Submicron NMOS Transistors

This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device fing...

متن کامل

Reliable CMOS VLSI Design Considering Gate Oxide Breakdown

As technology scales down into the nanometer region, the reliability mechanism caused by time dependent dielectric breakdown (TDDB) has become one of the major reliability concerns. TDDB can lead to performance degradation or logic failures in nanoscale CMOS devices, and can cause significant increase of leakage power in the standby mode. In this paper, the TDDB effects on the delay and power o...

متن کامل

Substrate Pick-Up Impacting on ESD Performances of Cascode NMOS Transistors

The cascode NMOS architecture has been tested by the Human Body Model (HBM), Machine Model (MM) and Transmission Line Pulse Generator (TLP) in this paper. For the TLP, detailed silicon data have been analyzed well in many parameters, such as the first triggeringon voltage (Vt1), the first triggering-on current (It1), the holding voltage (Vh), and the TLP I-V curve. Besides the above three kinds...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • Microelectronics Reliability

دوره 45  شماره 

صفحات  -

تاریخ انتشار 2005